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rev. 4118h?aero?06/03 f eatures integer unit based on sparc v7 high-performance risc architecture optimized integrated 32/64-bit floating-point unit on-chip peripherals ? edac and parity generator and checker ? memory interface chip select generator waitstate generation memory protection ?dma arbiter ?timers general purpose timer (gpt) real-time clock timer (rtct) watchdog timer (wdt) ? interrupt controller with 5 external inputs ? general purpose interface (gpi) ? dual uart speed optimized code ram interface 8- or 40-bit boot-prom (flash) interface ieee 1149.1 test access port (tap) for debugging and test purposes fully static design performance: 12 mips/3 mflops (double precision) at sysclk = 15 mhz core consumption: 1.0w typ. at 20 mips/0.7w typ. at 10 mips operating range: 4.5v to 5.5v (1) -55 c to +125 c total dose radiation capability (parametric and functional): 300 krads (si) seu event rate better than 3 e-8 error/component/day (worst case) latch-up immunity better than (let) 100 mev-cm 2 /mg quality grades: esa scc, qml q or v package: 256 mqfpf; bare die note: 1. for 3.3v capability see the tsc695fl datasheet on the atmel site. description the tsc695f (erc32 single-chip) is a highly integrated, high-performance 32-bit risc embedded processor implementing the sparc architecture v7 specification. it has been developed with the support of the esa (european space agency), and offers a full development environment for embedded space applications. the processor is manufactured using the atmel 0.5 m radiation tolerant ( 300 krads (si)) cmos enhanced process (rtp). it has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. the tsc695f includes an on-chip integer unit (iu), a floating point unit (fpu), a memory controller and a dma arbiter. for real-time applications, the tsc695f offers a high security watchdog, two timers, an interrupt controller, parallel and serial inter- faces. fault tolerance is supported using parity on internal/external buses and an edac on the external data bus. the design is highly testable with the support of an on-chip debugger (ocd), and a boundary scan through jtag interface. rad-hard 32-bit sparc embedded processor tsc695f
2 tsc695f 4118h ? aero ? 06/03 block diagram figure 1. tsc695f block diagram pin descriptions for pin assignment, refer to package section. general purpose interface uart a tap clock managt error managt general purpose timer real time clock timer 32-bit integer unit dma arbiter access controller address interface wait state controller interrupts rxd, txd gpi bits dma ctrl mem ctrl ready/busy add.+size+asi data+check bits parities edac watch dog parity parity gen./check. reset & uart b interrupt controller 32/64-bit floating-point unit parity gen./chk. gen./chk. table 1. pin descriptions signal type active description ra[31:0] i/o, 32-bit registered address bus output buffer: 400 pf rapar i/o high registered address bus parity - rasi[3:0] i/o 4-bit registered address space identifier - rsize[1:0] i/o 2-bit registered bus transaction size - raspar i/o high registered asi and size parity - cpar i/o high control bus parity - d[31:0] i/o 32-bit data bus - cb[6:0] i/o 7-bit check-bit bus - dpar i/o high data bus parity - rldsto i/o high registered atomic load-store - ale o low address latch enable - dxfer i/o high data transfer - lock i/o high bus lock - rd i/o high read access - we i/o low write enable - wrt i/o high advanced write - mhold o low memory bus hold mhold+fhold +bhold+fccv mds o low memory data strobe - mexc o low memory exception - prom8 i low select 8-bit wide prom - ba[1:0] o latched address used for 8-bit wide boot prom - romcs o low prom chip select - romwrt i low rom write enable - memcs[9:0] o low memory chip select output buffer: 400 pf memwr o low memory write strobe output buffer: 400 pf
3 tsc695f 4118h ? aero ? 06/03 note: if not specified, the output buffer type is 150 pf, the input buffer type is ttl. oe o low memory output enable output buffer: 400 pf buffen o low data buffer enable - ddir o high data buffer direction - ddir o low data buffer direction - iosel[3:0] o low i/o chip select - iowr o low i/o and exchange memory write strobe - exmcs o low exchange memory chip select - busrdy i low bus ready - buserr i low bus error - dmareq i low dma request - dmagnt o low dma grant - dmaas i high dma address strobe - drdy o low data ready during dma access - iuerr o low iu error - cpuhalt o low processor (iu & fpu) halt and freeze - syserr o low system error - syshalt i low system halt - sysav o high system availability - nopar i low no parity - inull o high integer unit nullify cycle - inst o high instruction fetch used to check the execute stage of iu instruction pipeline flush o high fpu instruction flush dia o high delay instruction annulled rtc o high real time clock counter output - rxa/rxb i receive data uart ? a ? and ? b ? input trigger txa/txb o transmit data uart ? a ? and ? b ? - gpi[7:0] i/o gpi input/output input trigger gpiint o high gpi interrupt - extint[4:0] i external interrupt input trigger extintack o high external interrupt acknowledge - iwde i high internal watch dog enable - ewdint i high external watch dog input interrupt input trigger wdclk i watch dog clock - clk2 i double frequency clock - sysclk o system clock - reset o low output reset - sysreset i low system input reset input trigger tmode[1:0] i factory test mode functional mode=00 debug i high software debug mode - tck i test (jtag) clock - trst i low test (jtag) reset pull-up 37 k ? tms i test (jtag) mode select pull-up 37 k ? tdi i test (jtag) data input pull-up 37 k ? tdo o test (jtag) data output - vcci/vssi main internal power - vcco/vsso output driver power - table 1. pin descriptions (continued) signal type active description
4 tsc695f 4118h ? aero ? 06/03 system architecture the tsc695f is to be used as an embedded processor requiring only memory and application specific peripherals to be added to form a complete on-board computer. all other system support functions are provided by the core. figure 2. system architecture based on tsc695f iu fpu memory ale sysclk a[31:0] ra[31:0] master ax[31:0] tsc695f dma unit local memory dmagnt dmareq dmaas ramctrl (romcs , exmcs , iosel [3:0], memwr , iowr , oe , busrdy ,...) d[31:0] (0 ws) ram cb[6:0] dpar boot prom xtd prom xchg mem xtd ram xtd i/o xtd general i/o 0 to i/o 3 memory glue logic dma dma (memcs [9:0], memwr , oe ) (buffen , ddir) interface user peripherals application memctrl
5 tsc695f 4118h ? aero ? 06/03 p roduct d escription integer unit the integer unit (iu) is designed for highly dependable space and military applications, and includes support for error detection. the risc architecture makes the creation of a processor that can execute instructions at a rate approaching one instruction per pro- cessor clock possible. to achieve that rate of execution, the iu employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. fetch - the processor outputs the instruction address to fetch the instruction. decode - the instruction is placed in the instruction register and is decoded. the processor reads the operands from the register file and computes the next instruction address. execute - the processor executes the instruction and saves the results in temporary registers. pending traps are prioritized and internal traps are taken during this stage. write - if no trap is taken, the processor writes the result to the destination register. all four stages operate in parallel, working on up to four different instructions at a time. a basic ? single-cycle ? instruction enters the pipeline and completes infour cycles. by the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. so, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. of course, a ? single-cycle ? instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can com- plete one instruction per cycle after the initial four-cycle delay. floating-point unit the floating point unit (fpu) is designed to provide execution of single and double- precision floating-point instructions concurrently with execution of integer instructions by the iu. the fpu is compliant to the ansi/ieee-754 (1985) floating-point standard. the fpu is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. the fpu uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (f, d, e and w). the fetch unit captures instructions and their addresses from the data and address buses. the decode unit contains logic to decode the floating- point instruction opcodes. the execution unit handles all instruction execution. the exe- cution unit includes a floating-point queue (fp queue), which contains stored floating- point operate (fpop) instructions under execution and their addresses. the execution unit controls the load unit, the store unit, and the datapath unit. the fpu depends upon the iu to access all addresses and control signals for memory access. floating-point loads and stores are executed in conjunction with the iu, which provides addresses and control signals while the fpu supplies or stores the data. instruction fetch for integer and floating-point instructions is provided by the iu. the fpu provides three types of registers: f registers, fsr, and the fp queue. the fsr is a 32-bit status and control register. it keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various ieee exception information. the floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address.
6 tsc695f 4118h ? aero ? 06/03 instruction set tsc695f instructions fall into six functional categories: load/store, arithmetic/logi- cal/shift, control transfer, read/write control register, floating-point, and miscellaneous. please refer to sparc v7 instruction-set manual. note: the execution of iflush will cause an illegal instruction trap. on-chip peripherals memory interface the tsc695f is designed to allow easy interfacing to internal/external memory resources. system registers the system registers are only writable by iu in the supervisor mode or by dma during halt mode. table 2. memory mapping memory contents start address size (bytes) data size and parity options boot prom 0x 0000 0000 128k 16m 8-bit mode no parity/-no edac/-only byte write 40-bit mode parity + edac mandatory/-only word write extended prom 0x 0100 0000 max: 15m 8-bit mode no parity/-no edac/-only byte write 40-bit mode parity + edac mandatory/-only word write exchange memory 0x 01f0 0000 4k 512k parity + edac option/-only word write system registers 0x 01f8 0000 512k (124 used) parity/-only word read/write access ram (8 blocks) 0x 0200 0000 8*32k 8*4m parity + edac option/-all data sizes allowed extended ram 0x 0400 0000 max: 192m i/o area 0 0x 1000 0000 0 16m parity option/-all data sizes allowed i/o area 1 0x 1100 0000 0 16m i/o area 2 0x 1200 0000 0 16m i/o area 3 0x 1300 0000 0 16m extended i/o area 0x 1400 0000 max: 1728m extended general 0x 8000 0000 max: 2g no parity/-all data sizes allowed table 3. system registers address map system register name address system control register sysctr 0x 01f8 0000 software reset swrst 0x 01f8 0004 power down pdown 0x 01f8 0008 system fault status register sysfsr 0x 01f8 00a0 failing address register failar 0x 01f8 00a4 error & reset status register errrsr 0x 01f8 00b0 test control register tesctr 0x 01f8 00d0
7 tsc695f 4118h ? aero ? 06/03 wait-state and time-out generator it is possible to control the wait-state generation by programming a wait-state configu- ration register. the maximum programmable number of wait-states is applied by default at reset. it is possible to program the number of wait-states for the following combinations: ? ram read and write ? prom read and write (i.e. eeprom or flash write) ? exchange memory read/write ? four individual i/o peripherals read/write a bus time-out function of 256 system clock cycles is provided for the bus ready con- trolled memory areas, i.e., the extended prom, exchange memory, extended ram, memory configuration register mcnfr 0x 01f8 0010 i/o configuration register iocnfr 0x 01f8 0014 waitstate configuration register wscnfr 0x 01f8 0018 access protection segment 1 base register aps1br 0x 01f8 0020 access protection segment 1 end register aps1er 0x 01f8 0024 access protection segment 2 base register aps2br 0x 01f8 0028 access protection segment 2 end register aps2er 0x 01f8 002c interrupt shape register intshr 0x 01f8 0044 interrupt pending register intpdr 0x 01f8 0048 interrupt mask register intmkr 0x 01f8 004c interrupt clear register intclr 0x 01f8 0050 interrupt force register intfcr 0x 01f8 0054 watchdog timer register wdogtr 0x 01f8 0060 watchdog timer trap door set wdogst 0x 01f8 0064 real time clock timer register rtccr 0x 01f8 0080 real time clock timer register rtcsr 0x 01f8 0084 general purpose timer register gptcr 0x 01f8 0088 general purpose timer register gptsr 0x 01f8 008c timers control register timctr 0x 01f8 0098 general purpose interface configuration register gpicnfr 0x 01f8 00a8 general purpose interface data register gpidatr 0x 01f8 00ac uart ? a ? rx & tx register uartar 0x 01f8 00e0 uart ? b ? rx & tx register uartbr 0x 01f8 00e4 uart status register uartsr 0x 01f8 00e8 table 3. system registers address map (continued) system register name address
8 tsc695f 4118h ? aero ? 06/03 extended i/o and the extended general areas. edac the tsc695f includes a 32-bit edac (error detection and correction). seven bits (cb[6:0]) are used as check bits over the data bus. the data bus parity signal (dpar) is used to check and generate the odd parity over the 32-bit data bus. this means that altogether 40 bits are used when the edac is enabled. the tsc695f edac uses a 7-bit hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. in addition, the edac detects all bits stuck-at- one and stuck-at-zero failure for any nibble in the data word as a non-correctable error. stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non- correctable error. memory and i/o parity the tsc695f handles parity towards memory and i/o in a special way. the processor can be programmed to use no parity, only parity or parity and edac protection towards memory and to use parity or no towards i/o. the signal used for the parity bit is dpar. memory redundancy programming the memory configuration register, the tsc695f provides chip selects for two redundant memory banks for replacement of faulty banks. memory access protection unimplemented areas - access to all unimplemented memory areas are handled by the tsc695f and detected as illegal. ram write access protection - the tsc695f can be programmed to detect and mask write accesses in any part of the ram. the protection scheme is enabled only for data area, not for the instruction area. the programmable write access protection is based on two segments. boot prom write protection - the tsc695f supports a qualified prom write for an 8-bit wide prom and/or for a 40-bit wide prom. dma dma interface the tsc695f supports direct memory access (dma). the dma unit requests access to the processor bus by asserting the dma request signal (dmareq ). when the dma unit receives the dmagnt signal in response, the processor bus is granted. in case the processor is in the power-down mode the processor is permanent tri-stated, and a dmareq will directly give a dmagnt . the tsc695f includes a dma session time-out function. bus arbiter the tsc695f always has the lowest priority on the system bus. traps a trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. the base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. two categories of traps can appear.
9 tsc695f 4118h ? aero ? 06/03 synchronous traps table 4. synchronous traps trap priority trap type (tt) comments reset 1 ? sources: sysreset* pin software reset watchdog reset iu or system error reset hardware error non-restartable, imprecise error 2 2.1 64h severe error requiring a re-boot tsc695f enters (if not masked) in halt or reset mode non-restartable, precise error 2.2 62h error not removable, pc & npc ok tsc695f enters (if not masked) in halt or reset mode register file error 2.3 65h special case of non-restartable, precise error. tsc695f enters (if not masked) in halt or reset mode restartable, late error 2.4 63h retrying instruction but pc & npc have to be re-adjusted tsc695f enters (if not masked) in halt or reset mode restartable, precise error 2.5 61h retrying instruction tsc695f enters (if not masked) in halt or reset mode instruction access ( error on instruction fetch ) 301h parity error on control bus parity error on data bus parity error on address bus access to protected or unimplemented area uncorrectable error in memory bus time out bus error illegal instruction 4 02h ? privileged instruction 5 03h ? fpu disabled 6 04h ? window overflow 7 05h during save instruction or trap taken underflow 06h during restore instruction or rett instruction memory address not aligned 8 07h ? fpu exception non-restartable error 9 9.1 08h severe error, cannot restart the instruction data bus error 9.2 parity error on fpu data bus restartable error 9.3 can be removed restarting the instruction sequence error 9.4 ? unimplemented fpop 9.5 ? ieee exceptions: 9.6 invalid operation division by zero overflow underflow inexact
10 tsc695f 4118h ? aero ? 06/03 it is possible to mask each individual interrupt (except watchdog time-out). the interrupts in the interrupt pending register are cleared automatically when the interrupt is acknowledged. by programming the interrupt shape register, it is possible to define the external interrupts to either be active low or active high and to define the external interrupts to either be edge or level sensitive. data access exception ( error on data load )1009h idem ? instruction access ? system register access violation tag overflow 11 0ah taddcctv and tsubcctv instructions trap instructions 12 80h to ffh trap on integer condition codes (ticc) table 4. synchronous traps (continued) trap priority trap type (tt) comments table 5. interrupts or asynchronous traps trap priority trap type (tt) comments watchdog time-out 13 1fh internal or external (ewdint pin) external int 4 14 1eh extintak on only one of extint[4:0] real time clock timer 15 1dh ? general purpose timer 16 1ch ? external int 3 17 1bh extintak on only one of extint[4:0] external int 2 18 1ah extintak on only one of extint[4:0] dma time-out 19 19h ? dma access error 20 18h ? uart error 21 17h ? correctable error in memory 22 16h data read ok but source not updated uart b data ready transmitter ready 23 15h ? uart a data ready transmitter ready 24 14h ? external int 1 25 13h extintak on only one of extint[4:0] external int 0 26 12h extintak on only one of extint[4:0] masked hardware errors 27 11h logical or of: iu hardware error masked iu error mode masked system hardware error masked
11 tsc695f 4118h ? aero ? 06/03 timers in software debug mode the timers are controlled by a system register bit and the exter- nal pin debug. general purpose timer the general purpose timer (gpt) provides, in addition to a generalized counter func- tion, a mechanism for setting the step size in which actual time counts are performed. gpt is clocked by the internal system clock. they are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. the current value of the scaler and counter of the gpt can be read. real time clock timer the only functional differences between the two timers are that the real time clock timer (rtct) has an 8-bit scaler (16-bit scaler for gpt) and that the rtct interrupt has higher priority than the gpt interrupt. rtct information is available on rtc output pin. watchdog timer setting the external pin iwde to v cc enables the internal watchdog timer. otherwise the watchdog function must be externally provided. the watchdog is supplied from a separate external input (wdclk). after reset, the timer is enabled and starts running with the maximum range. if the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. simulta- neously, the timer starts counting a reset time-out period. if the timer is not acknowledged before the reset time-out period elapses, a reset is applied to tsc695f. uarts two full duplex asynchronous receiver transmitters (uart) are included. in software debug mode the uart ? s are controlled by system register bits. the data format of the uart ? s is eight bits. it is possible to choose between even or odd parity, or no parity, and between one and two stop bits. the uart ? s provide double buff- ering, i.e. each uart consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. each of these registers are 8-bit wide. for each uart a rx and tx register is provided. the uart ? s generate an interrupt each time a byte has been received or a byte has been sent. there is another interrupt to indicate errors. the baud rate of both the uart ? s is programmable. the clock is derived either from the system clock or can use the watchdog clock. general purpose interface the general purpose interface (gpi) is an 8-bit parallel i/o port. each pin can be config- ured as an input or an output. a falling or rising edge detection is made on each selected gpi inputs. every input tran- sition on gpi generates an external positive pulse on gpiint pin of two sysclk width. execution modes reset mode reset mode is entered when: ? the sysres input is asserted ? software reset which is caused by the software writing to a software reset register ? watchdog reset which is caused by a watchdog counter time-out ? error reset which is caused by a hardware parity error
12 tsc695f 4118h ? aero ? 06/03 this reset output has a minimum of 1024 sysclk width to allow the usage of flash memories. the error and reset status register contain the source of the last processor reset. run mode in this mode the iu/fpu is executing, while all peripherals are running (if software enabled). system halt mode system halt mode is entered when the syshalt input is asserted. in this mode, the iu and fpu are frozen, while the timers (includeing the internal watchdog timer) and uart ? s are stopped. power down mode this mode is entered by writing to the power-down register. in this mode, the iu and fpu are frozen. the tsc695f leaves the power-down mode if an external interrupt is asserted. error halt mode error halt mode is entered under the following circumstances: ? a internal hardware parity error. ? the iu enters error mode. the only way to exit error halt mode is through cold reset by asserting sysreset . error handler the tsc695f has one error output signal (syserr ) which indicates that an unmasked error has occurred. any error signalled on the error inputs from the iu and the fpu is latched and reflected in the error and reset status register. by default, an error leads to a processor halt. parity checking the tsc695f includes: ? parity checking and generation (if required) on the external data bus ? parity checking on the external address bus ? parity checking on asi and size ? parity checking and generation on all system registers ? parity generation and checking on the internal control bus to the iu all external parity checking can be disabled using the nopar signal. system clock the tsc695f uses clk2 clock input directly and creates a system clock signal by dividing clk2 by two. it drives sysclk pin with a nominal 50% duty cycle for the appli- cation. it is highly recommended that only sysclk rising edge is used as reference as far as possible. system availability the sysav bit in the error and reset status register can be used by software to indi- cate system availability. test mode the tsc695f includes a number of software test facilities such as edac test, parity test, interrupt test, error test and a simple test access port. these test functions are controlled using the test control register.
13 tsc695f 4118h ? aero ? 06/03 test and diagnostic hardware functions a variety of tsc695f test and diagnostic hardware functions, including boundary scan, internal scan, clock control and on-chip debugger, are controlled through an ieee 1149.1 (jtag) standard test access port (tap). test access port the tap interfaces to the jtag bus via 5 dedicated pins on the tsc695f chip. these pins are: tck (input): test clock tms (input): test mode select tdi (input): test data input tdo (output): test data output trst (input): test reset instruction register five standard instructions are supported by the tsc695f tap. debugging the design is highly testable with the support of an on-chip debugger (ocd), an inter- nal and boundary scan through jtag interface. binary value name of instruction data register scan chain accessed 00. 0000 extest boundary scan register boundary scan chain 00. 0001 sample/preload boundary scan register boundary scan chain 00. 0011 intest boundary scan register boundary scan chain 11. 1111 bypass bypass register bypass register 10. 0000 idcode device id register id register scan chain
14 tsc695f 4118h ? aero ? 06/03 electrical characteristics absolute maximum ratings dc characteristics military range............................................... -55 c to +125 c storage temperature ..................................... -65 c to +150 c supply voltage...................................................-0.5v to +7.0v input voltage......................................................-0.5v to +7.0v note: stresses at or above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 6. dc characteristics at v dd 5v 10% symbol parameter min typ max unit test conditions vil trigger input low voltage for trigger input ?? 0.8 v v cc = 4.5 to 5.5v vih trigger input high voltage for trigger input 3.0 ?? vv cc = 4.5 to 5.5v ? vt input hysteresis for trigger input ? 0.9 ? vv cc = 4.5 to 5.5v vil ttl input low voltage for ttl input ?? 0.8 v v cc = 4.5 to 5.5v vih ttl input high voltage for ttl input 2.2 ?? vv cc = 4.5 to 5.5v vol 400 pf output low voltage for 400 pf buffer ? 0.3 0.4 v v cc = 4.5 to 5.5v iol = 12 ma voh 400 pf output high voltage for 400 pf buffer 2.4 0.3 ? v v cc = 4.5 to 5.5v ioh = -16 ma vol 150 pf output low voltage for 150 pf buffer ? 0.3 0.4 v v cc = 4.5 to 5.5v iol = 4 ma voh 150 pf output high voltage for 150 pf buffer 2.4 4.3 ? v v cc = 4.5 to 5.5v ioh = -6 ma icc op operating supply current for core processor ?? 230 ma v cc = 5.5v, f = 25 mhz ?? 210 v cc = 5.5v, f = 20 mhz ?? 170 v cc = 5.5v, f = 10 mhz icc pd power down supply current for core processor ?? 41 ma v cc = 5.5v, f = 25mhz ?? 38 v cc = 5.5v, f = 20 mhz ?? 30 v cc = 5.5v, f = 10 mhz
15 tsc695f 4118h ? aero ? 06/03 capacitance ratings ac characteristics parameter description max c in input capacitance 7 pf c out output capacitance 8 pf c io input/output capacitance 8 pf table 7. ac characteristics (sysclk freq. = 25 mhz ? 5v 10%) c load = 50 pf, v ref = 2.5 v parameter min (ns) max (ns) comment reference edge t1 20 ? clk2 period ? t2 40 ? sysclk period ? t3 9.75 ? clk2 high and low pulse width ? t4 ? 6.5 ra(31:0) rapar rsize rldsto output delay sysclk+ t5 ? 12.5 memcs*(9:0) romcs* exmcs* output delay sysclk+ t6 ? 15 ddir ddir* output delay sysclk+ t7 ? 23.5 memwr* iowr*output delay formula: 13.5 ns + 1 / 4 t2 sysclk- or sysclk+ t8 ? 20.5 oe* hl output delay formula: 10.5 ns + 1 / 4 t2 sysclk+ t9 t9_1 11.5 ? data setup time during load sysclk+ t9_2 9 ? data setup time during load mnopar = 0 rpa = rec = either 1 or 0 sysclk+ t10 5 ? data hold time during load sysclk+ t11 ? 28 data output delay sysclk- t12 8 ? data output valid to hz ? guaranteed by design sysclk+ t13 ? 19 cb output delay sysclk+ t14 ? 13 ale* output delay sysclk- t15 ? 21 buffen* hl output delay formula: 11 ns + 1 / 4 t2 sysclk+ t16 ? 15 mhold* output delay ? guaranteed by design sysclk+ t17 ? 15 mds* drdy* output delay sysclk+ t20 ? 15 mexc* output delay sysclk- t21 10 ? rasi(3:0) rsize(1:0) raspar setup time sysclk+ t22 3 ? rasi(3:0) rsize(1:0) raspar hold time sysclk+ t23 ? 13 boot prom address output delay sysclk+
16 tsc695f 4118h ? aero ? 06/03 t24 12 ? busrdy* setup time sysclk+ t25 0 ? busrdy* hold time sysclk+ t27 ? 15 iosel output delay sysclk+ hl sysclk- lh t28 12 20 dmaas setup time formula of max: 1 / 2 t2 sysclk+ t29 0 20 dmaas hold time formula of max: 1 / 2 t2 sysclk- t30 12 ? dmareq* setup time sysclk+ t31 ? 15 dmagnt* output delay sysclk+ t32 10 ? ra(31:0) rapar cpar setup time sysclk+ t33 3 ? ra(31:0) rapar cpar hold time sysclk+ t36 100 ? tck period - t37 10 ? tms setup time tck+ t38 4 ? tms hold time tck+ t39 10 ? tdi setup time tck+ t40 10 ? tdi hold time tck+ t41 ? 20 tdo output delay tck- t46 ? 22 inull output delay sysclk+ t48 ? 22 reset* cpuhalt* output delay sysclk+ t49 ? 20 syserr* sysav output delay sysclk+ t50 ? 20 iuerr* output delay sysclk+ t52 12 ? extint(4:0) setup time sysclk- t53 0 ? extint(4:0) hold time sysclk+ t54 ? 15 extintack output delay sysclk+ t56 ? 8.5 oe* lh output delay (no dma mode) sysclk+ t57 ? 9 buffen* lh output delay sysclk+ t60 ? 22 inst output delay sysclk+ t61 20 ? data output delay to low-z ? guaranteed by design formula: 10 ns + 1 / 4 t2 sysclk+ table 7. ac characteristics (sysclk freq. = 25 mhz ? 5v 10%) c load = 50 pf, v ref = 2.5 v (continued) parameter min (ns) max (ns) comment reference edge
17 tsc695f 4118h ? aero ? 06/03 figure 3. 150 pf buffer response (data from simulation)
18 tsc695f 4118h ? aero ? 06/03 figure 4. 400 pf buffer response (data from simulation)
19 tsc695f 4118h ? aero ? 06/03 figure 5. oe*/400 pf buffer response (data from simulation)
20 tsc695f 4118h ? aero ? 06/03 timing diagrams figure 6. ram fetch, ram load and ram store sequence - n waitstates for read, m waitstates for write 1 (ram fetch) 2 (ram load) 3 (ram fetch) 4 (ram store) 5 (ram fetch) t17 t17 t17 t17 t17 t17 t17 t16 t16 t60 t60 t60 t60 t12 t13 t61 t12 t11 t61 t12 t11 t61 t8 t56 t56 t8 t7 t7 t6 t6 t5 t5 t5 t5 t14 t14 t4_1 t4_1 t4_1 t4_1 n ws n ws m ws m ws n ws n ws n ws n ws n ws n ws t10 t9 t10 t9 t10 t9 t2 t2 t3 t3 t3 t3 t1 t1 fa1 fa2 la1 sa1 fa3 fd1 ld1 fd2 sd1 fd3 fp1 lp1 fp2 sp1 fp3 fc1 lc1 fc2 sc1 fc3 previous stored checkbyte previous stored data previous stored parity clk2 sysclk ra [31:0] ale memcs* [0] memcs* [1] romcs* ddir memwr* buffen* oe* d [31:0] dpar cb [6:0] inst mhold* mds*
21 tsc695f 4118h ? aero ? 06/03 figure 7. ram atomic-load-store byte sequence - 0 waitstate 1 (ram fetch) 2 (ram atomic load store) 3 (ram fetch) t4_2 t4_2 t4_1 t4_1 t46 t46 t16 t16 t60 t60 t12 t13 t61 t12 t11 t61 t12 t11 t61 t8 t56 t8 t56 t8 t7 t7 t6 t6 t6 t6 t5 t5 t5 t5 t4_1 t4_1 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t2 t2 fa1 alsa fd1 byte from ram word from ram word to ram fa5 fp1 fp5 fd5 fc1 fc5 held to update the full word parity from ram checkbyte from ram parity to ram checkbyte to ram parity from ram checkbyte from ram sysclk ra [31:0] ale* memcs* [0] memcs* [1] ddir memwr* buffen* oe* d [31:0] dpar cb [6:0] inst mhold* mds* inull rldsto lock
22 tsc695f 4118h ? aero ? 06/03 figure 8. ram load-double and ram store-double sequence - 0 waitstate 1 (ram fetch) 2 (ram double load) 3 (ram fetch) 4 (ram double store) 5 (ram fetch) t4_2 t4_2 t46 t46 t16 t16 t60 t60 t12 t13 t13 t61 t12 t11 t11 t61 t12 t11 t11 t61 t8 t56 t8 t56 t8 t7 t7 t7 t7 t6 t6 t5 t5 t5 t5 t5 t5 t5 t5 t4_1 t4_1 t4_1 t4_1 t4_1 t4_1 t10 t9 t10 t9 t10 t9 t2 t2 fa1 la1 la2 fa2 sa1 sa2 fa3 fd1 ld1 ld2 fd2 sd1 sd2 fd3 fp1 lp1 lp2 fp2 sp1 sp2 fp3 fc1 lc1 lc2 fc2 sc1 sc2 fc3 sysclk ra [31:0] ale* memcs* [0] memcs* [1] ddir memwr* buffen* oe* d [31:0] dpar cb [6:0] inst mhold* mds* inull lock
23 tsc695f 4118h ? aero ? 06/03 figure 9. ram load with correctable error - 0 waitstate 1 (ram fetch) 2 (ram load correctable data) 3 (ram fetch) 4 (ram fetch) t60 t60 t17 t17 t16 t16 t8 t56 t56 t8 t5 t5 t5 t5 t4_1 t4_1 t4_1 t14 t14 internal error correction internal error correction load load t10 t9 t10 t9 t2 t2 fd1 ld1 fd2 fd2 fd3 fa1 la1 fa2 fa3 fc1 lc1 fc2 fc2 fc3 fp1 lp1 fp2 fp2 fp3 1-bit error on 40-bit data sysclk ale* ra[31-0] memcs*[0] memcs*[1] ddir memwr* iowr* oe* buffen* d[31-0] cb[6-0] dpar mhold* mexc* mds* inst inull data correction made inside
24 tsc695f 4118h ? aero ? 06/03 figure 10. ram load with uncorrectable error - 0 waitstate 1 (ram fetch) 2 (ram load) 3 (ram fetch) 4 (null cycle) 5 (ram fetch) 6 (ram fetch) t46 t46 t60 t60 t60 t60 t17 t17 t20 t20 t16 t16 t56 t8 t56 t8 t5 t5 t5 t5 t4_1 t4_1 t4_1 t4_1 t14 t14 trap trap exception internal error detection internal error detection load load t10 t9 t10 t9 t2 t2 fa1 ld1 fa2 fa3 ta1 ta2 fd1 ld1 fd2 fd2 fd2 fd3 td1 td2 2-bit error on 40-bit data fc1 lc1 fc2 fc2 fc2 fc3 tc1 tc2 fp1 lp1 fp2 fp2 fp2 fp3 tp1 tp2 sysclk ale* ra[31-0] memcs*[0] memcs*[1] ddir memwr* iowr* oe* buffen* d[31-0] cb[6-0] dpar mhold* mexc* mds* inst inull
25 tsc695f 4118h ? aero ? 06/03 figure 11. ram load with unimplemented area access - 0 waitstate 1 (ram fetch) 2 (ram load) 3 (ram fetch) 4 (null cycle) 5 (ram fetch) 6 (ram fetch) t46 t46 t60 t60 t60 t60 t17 t17 t20 t20 t16 t16 t56 t8 t8 t56 t5 t5 t4_1 t4_1 trap trap fetch fetch internal error internal error t10 t9 t10 t9 t2 t2 unimplemented address fa1 la1 fa2 fa3 ta1 ta2 no data fd1 fd2 fd3 td1 td2 sysclk ale* ra[31-0] memcs*[0] memcs*[1] ddir memwr* iowr* buffen* oe* d[31-0] mhold* mexc* mds* inst inull
26 tsc695f 4118h ? aero ? 06/03 figure 12. i/o store sequence with busrdy* and n waitstates (timing for 0 waitstate = timing for 1 waitstates) 1 (ram fetch) 2 (i/o store) 3 (ram fetch) t16 t16 t60 t60 t12 t11 t61 t8 t56 t57 t15 t7 t7 t6 t6 t27 t27 t5 t5 t4_1 t4_1 t4_1 end of cycle rdy waiting (n-1) ws start of cycle t10 t9 t25 t24 t24 t2 t2 fa1 sa1 fa2 fd1 fd2 sd1 previous stored data sysclk ale* ra[31-0] memcs*[0] iosel*[0] busrdy* ddir memwr* iowr* buffen* oe* d[31-0] inst mhold* mds*
27 tsc695f 4118h ? aero ? 06/03 figure 13. i/o load sequence with busrdy* and n waitstates (timing for 0 ws = timing for 1 ws) 1 (ram fetch) 2 (i/o load) 3 (ram fetch) t17 t17 t16 t16 t60 t60 t8 t56 t8 t56 t57 t15 t27 t27 t5 t5 t4_1 t4_1 t14 t14 end of cycle end of cycle rdy waiting rdy waiting (n-1) ws start of cycle t10 t9 t10 t9 t25 t24 t24 t2 t2 fa1 la1 fa2 fd1 fd2 ld1 data driven by external buffers (c.f buffen*) sysclk ale* ra[31-0] memcs*[0] iosel*[0] busrdy* ddir memwr* iowr* buffen* oe* d[31-0] inst mhold* mds*
28 tsc695f 4118h ? aero ? 06/03 figure 14. exchange ram store with busdry* and n waitstates 1 (ram fetch) 2 (xchgram store) 3 (ram fetch) t16 t16 t60 t60 t12 t11 t61 t8 t56 t57 t15 t7 t7 t7 t7 t6 t6 t5 t5 t5 t5 t4_1 t4_1 end of cycle end of cycle n ws n ws in between in between rdy waiting rdy waiting start of cycle start of cycle t25 t24 t24 t2 t2 previous stored data fa1 sa1 fa2 fd1 sd1 fd2 sysclk ale* ra[31-0] memcs*[0] exmcs* ddir memwr* iowr* buffen* oe* busrdy* d[31-0] inst mhold* mds*
29 tsc695f 4118h ? aero ? 06/03 figure 15. exchange ram load with busdry* and n waitstates 1 (ram fetch) 2 (xchgram load) 3 (ram fetch) t17 t17 t16 t16 t60 t60 t8 t56 t57 t15 t5 t5 t5 t5 t4_1 t4_1 t14 t14 end of cycle end of cycle n ws n ws rdy waiting rdy waiting start of cycle start of cycle t10 t9 t25 t24 t24 t2 t2 fa1 la1 fa2 fd1 ld1 fd2 data driven by external buffers (c.f buffen*) sysclk ale* ra[31-0] memcs*[0] exmcs* ddir memwr* iowr* buffen* oe* busrdy* d[31-0] inst mhold* mds*
30 tsc695f 4118h ? aero ? 06/03 figure 16. 8-bit boot prom fetch (or load word) - n waitstates 1 (rom fetch) 2 (8-bit rom fetch or load word) 3 (rom fetch) t17 t17 t17 t16 t16 t16 t60 t60 t8 t56 t8 t15 t57 t15 t5 t5 t5 t23 t23 t23 t23 t4_1 t4_1 t4_1 t4_1 t4 t14 (n-1) ws end of byte 3 (n-1) ws (n-1) ws byte 3 byte 2 (n-1) ws (n-1) ws byte 2 byte 1 (n-1) ws (n-1) ws byte 1 byte 0 (n-1) ws byte 0 start of t10 t10 t9 t10 t9 t10 t9 t9 t2 t2 01 2 30 10 (address mod. 4) fd2-0 fd2-1 fd2-2 fd2-3 data driven by external buffers (c.f buffen*) fa2 (1 = fetch, 0 = load word) fa1 fa2 sysclk ale* rsize[0,1] ra[31-0] ba[0,1] romcs* memcs*[0] ddir memwr* buffen* oe* d[31-8] d[7-0] inst mhold* mds* cycle cycle
31 tsc695f 4118h ? aero ? 06/03 figure 17. 8-bit boot prom 2x store byte - n waitstate 1 (ram fetch) 2 (8-bit rom write) 3 (ram fetch) 4 (8-bit rom write) 5 (ram fetch) t16 t16 t16 t16 t60 t60 t60 t12 t11 t61 t12 t11 t61 t56 t8 t56 t57 t15 t57 t15 t7 t7 t7 t7 t6 t6 t6 t6 t5 t5 t5 t5 t5 t5 t5 t5 t4_1 t4_1 t4_1 t4_1 t23 t23 t4_1 t4_1 t4_1 t4_1 (n-1) ws (n-1) ws start of (n-1) ws (n-1) ws start of t9 t9 t2 t2 addr.=mod. 4 addr.=mod. 4 +1 byte d[7:0] 00 01 10 00 00 10 10 byte d[7:0] 00 fa1 sa1 fa2 sa2 fa3 fd1 sd1 fd2 sd2 sysclk ale* ra[31-0] ba[0,1] rsize[0,1] memcs*[0] romcs* ddir memwr* iowr* buffen* oe* d[31-0] inst mhold* mds* cycle cycle
32 tsc695f 4118h ? aero ? 06/03 figure 18. dma ram load with or without correctable error and dma ram store - 0 waitstates 1 (ram fetch) 2 (ram fetch) 3 (dma session) 4 (ram fetch) 5 (ram fetch) t16 t16 t13 t13 t13 t13 t12 t11 t12 t11 t6 t6 t7 t7 t56 t8 t56 t8 t17 t17 t17 t17 t5 t5 t5 t5 t5 t31 t31 t31 t31 t31 t31 t4_1 t4_1 t4_1 t4_1 t4_1 t4_1 t4_1 t4_1 t4_1 t14 t14 t14 t14 cont ? lead-out nth dma store (0 ws) (0 cycle min) nth dma store (0 ws) 1st dma load (0 ws) (0 cycle min) 1st dma load (0 ws) lead-in lead-in (null cycle) t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t10 t9 t33 t32 t33 t32 t33 t32 t33 t32 t29 t28 t29 t28 t30 t30 t22 t21 t22 t21 t22 t21 t22 t21 t33 t32 t33 t32 t2 t2 fa1 (held to the end of ram access) fd1 d ld1 fa2 d san fa2 fd2 fa3 (from ram) d ld1 (from tsc695f) d la1 fc1 d lc1 fc2 (from ram) fp1 d lp1 fp2 (from ram) d lp1 (from tsc695f) fs1 fs2 d ssn fs2 fs3 d ls1 fz1 fz2 1 0 fz2 fz3 1 0 (only word access) early time for dmareq* desassertion (held to the end of ram access) parity generated by tsc695f if dpe =1, else, same timing as d[31-0] d sdn dspn d scn (pull-up on we*) sysclk ale* ra[31-0] rasi[3-0] rsize[1-0] dmareq* dmagnt* dmaas rd wrt memcs*[9-0] drdy* oe* memwr* ddir d[31-0] dpar cb[7-0] mhold* (held to the end of ram access) (only word access) corrected data if needed corrected parity if needed
33 tsc695f 4118h ? aero ? 06/03 figure 19. edge triggered interrupt timing fa(-1) fa0 fa1 fa2 fa3 fa4 tta0 tta1 tsa0 tsa1 tsa2 fd(-1) fd0 fd1 fd2 fd3 fd4 td0 td1 tsd0 tsd1 t54 t54 taken taken prioritized prioritized latched latched sampled sampled t53 t52 sysclk ra[31:0] ale* d[31:0] inull extint[i] extintack
34 tsc695f 4118h ? aero ? 06/03 figure 20. halt timing fan-1 fan fan+1 fan+1 fan+2 09h 09h 09h 09h 09h 10 10 10 10 10 fdn-1 fdn fdn+1 fdn+2 t48 t48 t49 t49 t16 t16 t14 t14 sysclk ra[31:0] rasi[3:0] rsize[1:0] ale* syshalt* mhold* sysav cpuhalt* d[31:0]
35 tsc695f 4118h ? aero ? 06/03 figure 21. external error with halt timing fan-1 fan fan+1 09h 09h 09h 10 10 10 fdn-1 fdn t48 t49 t16 t49 t50 t50 t14 sysclk ra[31:0] rasi[3:0] rsize[1:0] ale* iuerr* syserr* mhold* sysav cpuhalt* d[31:0]
36 tsc695f 4118h ? aero ? 06/03 figure 22. reset timing fa n fa n+1 0h 4h 8h t48 t48 t47 t46 t14 t14 sysclk sysreset* ra[31:0] rasi[3:0] rsize[1:0] ale* inull reset*
37 tsc695f 4118h ? aero ? 06/03 package description thermal characteristics the thermal performance of a package is measured by its ability to dissipate the power required by the device into its surroundings. the electrical power drawn by the device generates heat on the top surface of the die. this heat is conducted through the pack- age to the surface and then transferred when there is surrounding air by convection. each heat transfer step has corresponding resistance, when there is surrounding air, to the heat flow, which is given the value r , the thermal resistance coefficient. subscripts are added to the coefficient to specify the two points that the heat is transferred between. commonly used coefficients are r ja (junction to ambient air), r jc (junction to case) and r ca (case to ambient). an electrical analogy can be made, as shown in figure 23, to illustrate the heat flow of a package. the heat transfer can be characterized mathematically by the following equation: ? where: ? p = device operating power (watts) tj = temperature of a junction on the device ( c) ta = temperature of the surrounding ambient air ( c) r ja = r jc + r ca in c/w figure 23. thermal model table 8. thermal characteristics r - value unit conditions temperature air ja 20 ~ 23 c/w 25/90 c blown air jc 0.4 ja 31 ~ 41 stationary air jc 0.4 tj ta ? pr ja = r ca package cavity die heat flow r ja r jc
38 tsc695f 4118h ? aero ? 06/03 256-lead mqfp-f package
39 tsc695f 4118h ? aero ? 06/03 256-lead mqfp-f pin assignments table 9. pin assignments pin signal pin signal pin signal pin signal 1 gpiint 65 d[0] 129 ra[0] 193 dxfer 2 gpi[7] 66 rsize[1] 130 vcco 194 mexc 3 vcco 67 rsize[0] 131 vsso 195 vcco 4 vsso 68 rasi[3] 132 rapar 196 vsso 5 gpi[6] 69 vcco 133 raspar 197 reset 6 gpi[5] 70 vsso 134 dpar 198 sysreset 7 gpi[4] 71 rasi[2] 135 vcco 199 ba[1] 8 gpi[3] 72 rasi[1] 136 vsso 200 ba[0] 9 vcco 73 rasi[0] 137 sysclk 201 cb[6] 10 vsso 74 ra[31] 138 tdo 202 cb[5] 11 gpi[2] 75 ra[30] 139 trst 203 vcco 12 gpi[1] 76 vcco 140 tms 204 vsso 13 gpi[0] 77 vsso 141 tdi 205 cb[4] 14 d[31] 78 ra[29] 142 tck 206 cb[3] 15 d[30] 79 ra[28] 143 clk2 207 cb[2] 16 vcco 80 ra[27] 144 drdy 208 cb[1] 17 vsso 81 vcco 145 dmaas 209 vcco 18 d[29] 82 vsso 146 vcco 210 vsso 19 d[28] 83 ra[26] 147 vsso 211 cb[0] 20 vcci 84 ra[25] 148 dmagnt 212 ale 21 vssi 85 ra[24] 149 exmcs 213 vcci 22 d[27] 86 vcci 150 vcci 214 vssi 23 d[26] 87 vssi 151 vssi 215 prom8 24 vcco 88 vcco 152 dmareq 216 romcs 25 vsso 89 vsso 153 buserr 217 memcs[9] 26 d[25] 90 ra[23] 154 busrdy 218 vcco 27 d[24] 91 ra[22] 155 romwrt 219 vsso 28 d[23] 92 ra[21] 156 nopar 220 memcs[8] 29 d[22] 93 vcco 157 syshalt 221 memcs[7] 30 vcco 94 vsso 158 cpuhalt 222 memcs[6] 31 vsso 95 ra[20] 159 vcco 223 memcs[5] 32 d[21] 96 ra[19] 160 vsso 224 memcs[4] 33 d[20] 97 ra[18] 161 syserr 225 memcs[3] 34 d[19] 98 vcco 162 sysav 226 vcco 35 d[18] 99 vsso 163 extint[4] 227 vsso
40 tsc695f 4118h ? aero ? 06/03 36 vcco 100 ra[17] 164 extint[3] 228 memcs[2] 37 vsso 101 ra[16] 165 extint[2] 229 memcs[1] 38 d[17] 102 ra[15] 166 extint[1] 230 memcs[0] 39 d[16] 103 vcco 167 extint[0] 231 vcci 40 vcci 104 vsso 168 vcci 232 vssi 41 vssi 105 ra[14] 169 vssi 233 oe 42 d[15] 106 vcci 170 extintack 234 vcco 43 d[14] 107 vssi 171 iuerr 235 vsso 44 vcco 108 ra[13] 172 vcco 236 memwr 45 vsso 109 ra[12] 173 vsso 237 buffen 46 d[13] 110 vcco 174 cpar 238 ddir 47 d[12] 111 vsso 175 txa 239 vcco 48 d[11] 112 ra[11] 176 rxa 240 vsso 49 d[10] 113 ra[10] 177 rxb 241 ddir 50 vcco 114 ra[9] 178 txb 242 mhold 51 vsso 115 vcco 179 iowr 243 mds 52 d[9] 116 vsso 180 iosel[3] 244 wdclk 53 d[8] 117 ra[8] 181 vcco 245 iwde 54 d[7] 118 ra[7] 182 vsso 246 ewdint 55 d[6] 119 ra[6] 183 iosel[2] 247 tmode[1] 56 vcco 120 vcco 184 iosel[1] 248 tmode[0] 57 vsso 121 vsso 185 iosel[0] 249 debug 58 d[5] 122 ra[5] 186 wrt 250 inull 59 d[4] 123 ra[4] 187 we 251 dia 60 d[3] 124 ra[3] 188 vcco 252 vcco 61 d[2] 125 vcco 189 vsso 253 vsso 62 vcco 126 vsso 190 rd 254 flush 63 vsso 127 ra[2] 191 rldsto 255 inst 64 d[1] 128 ra[1] 192 lock 256 rtc table 9. pin assignments (continued) pin signal pin signal pin signal pin signal
41 tsc695f 4118h ? aero ? 06/03 ordering information table 10. possible order entries part-number supply voltage temperature range maximum speed (mhz) packaging quality flow tsc695f-25ma-e 5v 25 c 25 mqfp-f256 engineering samples tsc695f-25ma 5v -55 to +125 c 25 mqfp-f256 standard mil. 5962-0054001qxc 5v -55 to +125 c 25 mqfp-f256 qml-q 5962-0054001vxc 5v -55 to +125 c 25 mqfp-f256 qml-v TSC695F-25SASB 5v -55 to +125 c 25 mqfp-f256 scc b tsc695f-25mb-e 5v 25 c 25 die engineering samples 5962-0054001q9a 5v -55 to +125 c25 dieqml-q 5962-0054001v9a 5v -55 to +125 c25 dieqml-v
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4118h ? aero ? 06/03 /xm ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trade- marks of atmel corporation or its subsidiaries. other terms and product names may be the trademarks of oth- ers.

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